Silicon Photonics, LPO/LRO and NPO/CPO: Global Market
報告摘要
Silicon photonics builds optical functions — the generation, modulation, routing, and detection of light — directly onto silicon chips using the same fabrication infrastructure that produces conventional electronics. For most of its history the technology was understood as an efficiency improvement: a way to move data faster and with less power than copper allows. By 2026 that framing no longer captures the market. Artificial intelligence and high-performance computing require enormous volumes of data to move at tremendous speed between chips, servers, and racks, and current accelerator architectures have pushed copper interconnect to its physical limits. The result is an interconnect bottleneck, in which expensive, power-hungry accelerators sit idle waiting for data rather than computing. Silicon photonics has become the industry's structural answer, moving information in photons rather than electrons — photons travel faster, lose far less signal over distance, and carry more information per channel. Optical transceivers remain the application that drives the industry. Data rates have doubled every few years — 100G, 200G, 400G, 800G — and 2026 saw the commercialisation of 1.6-terabit transceivers, with 3.2T expected to sample around 2027 and 6.4T following in the early 2030s. As rates climb, even the short copper trace between an optical engine and the switch or accelerator ASIC limits performance, which is why co-packaged optics (CPO) and near-package optics (NPO) — moving the optical engine onto the ASIC substrate — have become the central packaging story of the decade, alongside linear-drive pluggable and receive optics (LPO/LRO) that strip power-hungry DSP from the link.
A fundamental constraint shapes the whole market: silicon's indirect bandgap means a practical pure-silicon laser cannot be built, which has spawned an ecosystem of complementary material platforms — III-V, lithium niobate, silicon nitride, polymer, plasmonic — and heterogeneous-integration techniques. Beyond datacom, photonic quantum computing has matured into a credible commercial segment, attracting roughly US$2.1 billion in private capital in 2025 and overtaking superconducting systems, thanks to room-temperature operation and CMOS-foundry compatibility. Further demand comes from telecommunications, FMCW LiDAR and sensing, and biomedical uses.
Silicon Photonics, LPO/LRO and NPO/CPO: Global Market 2027-2037 is a comprehensive market and technology assessment of the silicon-photonics and photonic-integrated-circuit (PIC) industry across the 2027–2037 forecast period. It arrives at an inflection point: with copper interconnect exhausted and AI infrastructure demanding unprecedented bandwidth, silicon photonics has shifted from an efficiency improvement to the structural foundation of next-generation data movement. The report frames the market around its two demand engines — AI-driven data communications and the newly commercial photonic-quantum segment — and quantifies the transition to co-packaged optics (CPO), near-package optics (NPO), and linear-drive pluggable and receive optics (LPO/LRO).
The analysis pairs detailed technology explanation with granular, segmented forecasts. Beyond datacom, the report covers competing and complementary platforms, the "copper wall" and beachfront-density crisis, manufacturing challenges and the capacity shift to Southeast Asia, divergent CPO ecosystems (NVIDIA vs. Broadcom) and the TSMC COUPE platform, and application markets spanning telecommunications, AI and computing, quantum, LiDAR and sensing, biomedical, instrumentation, defence, and microwave photonics. It includes an ecosystem market map, regional analysis, and 160 detailed company profiles, making it a decision-grade reference for investors, chip and system vendors, hyperscalers, foundries, and component suppliers navigating the interconnect transition.
Content covered includes:
Market sizing and 2027–2037 forecasts on both CPO and broad-market bases, with base/bull/bear scenarios, unit shipments, and CAGRs
Silicon-photonics technology primer: PICs, optical I/O and couplers, lasers and photon sources, photodetectors, III-V integration, modulators and Mach-Zehnder interferometers, waveguides, and optical-component density
Transceiver evolution roadmap (100G → 1.6T → 3.2T → 6.4T): form factors, process nodes, power, and cost-per-Gbps
CPO, NPO, and LPO/LRO architectures; scale-out vs. scale-up; NVIDIA and Broadcom ecosystems; TSMC COUPE packaging
Competing/complementary platforms: III-V, lithium niobate, silicon nitride, polymer, metaphotonics, and plasmonics
Structural themes: the copper wall and beachfront-density crisis, photonic AI acceleration, and the manufacturing shift to Southeast Asia
Application segments: data communications, telecommunications, AI & computing, quantum, LiDAR & sensing, biomedical, instrumentation & metrology, defence & aerospace, energy & industrial, consumer, and microwave photonics
Manufacturing, packaging, coupling, yield, and supply-chain challenges
Regional analysis (North America, Asia-Pacific, Europe, RoW) and research institutes
Ecosystem market map and 160 company profiles across the value chain including Accelink Technologies, Aeva Technologies, AEPONYX, Advantest, AIM Photonics, AIO Core, Alibaba Cloud, Amazon (AWS), ANSYS, Advanced Micro Foundry (AMF), Amkor Technology, AMO GmbH, Analog Photonics, Anello Photonics, Aryballe, ASE Technology Holdings, Aurora Innovation, Avicena, Axalume, Ayar Labs, Baidu, Bay Photonics, BE Epitaxy Semiconductor, Broadcom, Black Semiconductor, Broadex Technologies, CamGraPhIC, CEA-Leti, Centera Photonics, Cambridge Industries Group (CIG), Cisco, Coherent, CompoundTek, Crealights Technology, Credo Technology Group, CyberRidge, DenseLight, EFFECT Photonics, Eoptolink, Ephos, Fabrinet, Fast Photonics, Shenzhen Fibertop Technology, ficonTEC, FOCI (Fiber Optical Communication Inc.), FormFactor, Fujitsu, Genalyte, Gigalight, GlobalFoundries, Guangzhou CanSemi Technology, HGGenuine, Hisense Broadband Multimedia Technologies, HyperLight, HyperPhotonix, ICON Photonics, Intel, imec, Infleqtion, iPronics, JCET Group, Ki3 Photonics and more
授權報價
| Single User | $1,100 GBP |
目錄 Table of Contents
1 PURPOSE AND SCOPE 35
2 EXECUTIVE SUMMARY 36
2.1 Market Overview 36
2.2 Electronic and Photonic Integration Compared 40
2.3 Silicon Photonic Transceiver Evolution 40
2.4 Market Map 41
2.5 Global Market Trends in Silicon Photonics 44
2.6 Competing and Complementary Photonics Technologies 45
2.6.1 Metaphotonics 48
2.6.2 III-V Photonics 48
2.6.3 Lithium Niobate Photonics 48
2.6.4 Polymer Photonics 48
2.6.5 Plasmonic Photonics 49
2.7 Potential of Photonic AI Acceleration 49
2.8 The Copper Wall and the Beachfront-Density Crisis 50
2.9 Manufacturing Capacity Shifts to Southeast Asia 50
2.10 Commercial deployment of silicon photonics 50
2.11 Co-Packaged Optics 52
2.11.1 Divergent CPO Ecosystems: NVIDIA and Broadcom 52
2.11.2 The TSMC COUPE Packaging Platform 52
2.12 Manufacturing challenges 52
2.13 The Market Opportunity 55
2.14 Regional Strengths & Research Focus 55
3 INTRODUCTION TO SILICON PHOTONICS 56
3.1 What is Silicon Photonics? 56
3.1.1 Definition and Principles of Silicon Photonics 56
3.1.2 Comparison with traditional technologies 57
3.1.3 Silicon and Photonic Integrated Circuits 60
3.1.4 Optical IO, Coupling and Couplers 63
3.1.5 Emission and Photon Sources/Lasers 64
3.1.6 Detection and Photodetectors 64
3.1.7 Compound Semiconductor Lasers and Photodetectors (III-V) 65
3.1.8 Modulation, Modulators, and Mach-Zehnder Interferometers 66
3.1.8.1 New modulator technologies 67
3.1.9 Light Propagation and Waveguides 68
3.1.10 Optical Component Density 69
3.2 Advantages of Silicon Photonics 70
3.3 Applications of Silicon Photonics 70
3.4 Comparison with Other Photonic Integration Technologies 71
3.5 Evolution from Electronic to Photonic Integration 72
3.6 Silicon Photonics vs Traditional Electronics 73
3.7 Modern high-performance AI data centers 74
3.8 Core Technology Components 77
3.8.1 Optical IO, Coupling and Couplers 77
3.8.2 Emission and Photon Sources/Lasers 78
3.8.2.1 III-V Integration Challenges 79
3.8.2.2 Laser Integration Approaches 79
3.8.3 Detection and Photodetectors 80
3.8.4 Modulation Technologies 80
3.8.4.1 Mach-Zehnder Interferometers 81
3.8.4.2 Ring Modulators 81
3.8.4.3 Micro-Ring Modulators as a Competitive Differentiator 82
3.8.5 Light Propagation and Waveguides 82
3.8.6 Optical Component Density 82
3.9 Basic Optical Data Transmission 84
4 MATERIALS AND COMPONENTS 86
4.1 Silicon 86
4.1.1 Silicon as a Photonic Material 86
4.1.1.1 Optical Properties of Silicon 87
4.1.1.2 Fabrication Processes for Silicon Photonics 87
4.1.2 Silicon-on-insulator (SOI) 88
4.1.2.1 SOI Manufacturing Process 92
4.1.2.2 Key SOI Players 95
4.2 Germanium 96
4.2.1 Germanium Integration in Silicon Photonics 96
4.2.2 Germanium Photodetectors 96
4.2.3 Germanium-on-Silicon Modulators 97
4.3 Silicon Nitride 97
4.3.1 Silicon Nitride (SiN) in Photonics Integrated Circuits 97
4.3.2 Optical Properties and Fabrication of SiN 99
4.3.3 SiN Modulator Technologies 99
4.3.4 SiN Applications in Photonics Integrated Circuits 100
4.3.5 Advances in SiN Modulator Technologies 101
4.3.6 SiN-based Waveguides and Devices 101
4.3.7 SiN Performance Analysis 102
4.3.8 Applications of SiN in Photonics 103
4.3.9 SiN PIC Players 103
4.3.10 SiN Key Foundries 106
4.4 Thin Film Lithium Niobate (TFLN) 109
4.4.1 Overview 109
4.4.2 Lithium Niobate on Insulator (LNOI) 110
4.4.2.1 Overview of LNOI Technology 110
4.4.2.2 Characteristics and Properties of LNOI 111
4.4.2.3 LNOI Fabrication Processes 111
4.4.2.4 LNOI-based Modulator and Switch Technologies 112
4.4.2.5 Trends Toward Higher Speed and Improved Power Efficiency 112
4.4.2.6 High-Speed LNOI Modulators 113
4.4.2.6.1 Energy-Efficient LNOI Devices 114
4.4.2.6.2 Emerging LNOI Device Technologies 114
4.5 Indium Phosphide 115
4.5.1 Indium Phosphide (InP) Integration 115
4.5.1.1 InP as a Direct Bandgap Semiconductor 115
4.5.1.2 InP-based Active Components 116
4.5.1.3 Hybrid Integration of InP with Silicon Photonics 116
4.5.2 InP PIC Players 116
4.6 Barium Titanite and Rare Earth metals 117
4.6.1 Barium Titanate (BTO) Modulators 118
4.7 Organic Polymer on Silicon 119
4.7.1 Polymer-based Modulators 120
4.8 Wafer Processing 120
4.8.1 Wafer Sizes by Platform 120
4.8.2 Processing Challenges 121
4.8.3 Yield Management 121
4.9 Hybrid and Heterogeneous Integration 122
4.9.1 Monolithic Integration 122
4.9.2 Hybrid Integration 123
4.9.3 Heterogeneous Integration 123
4.9.4 III-V-on-Silicon 123
4.9.5 Bonding and Die-Attachment Techniques 123
4.9.6 Monolithic versus Hybrid Integration 124
5 ADVANCED PACKAGING TECHNOLOGIES 126
5.1 Evolution of Packaging Technologies 126
5.1.1 Traditional Packaging Approaches 129
5.1.2 Advanced Packaging Roadmap 130
5.1.3 Key Performance Metrics 132
5.2 2.5D Integration Technologies 133
5.2.1 Silicon Interposer Technology 134
5.2.2 Organic Substrate Options 136
5.3 3D Integration Approaches 136
5.3.1 Through-Silicon Via (TSV) 137
5.3.1.1 TSV Manufacturing Process 138
5.3.1.2 TSV Challenges and Solutions 139
5.3.2 Hybrid Bonding Technologies 140
5.3.2.1 Cu-Cu Bonding 141
5.3.2.2 Direct Bonding 141
5.4 Co-Packaged Optics (CPO) 142
5.4.1 CPO Architecture Overview 142
5.4.2 Benefits and Challenges 142
5.4.3 Integration Approaches 144
5.4.3.1 2D Integration 144
5.4.3.2 2.5D Integration 145
5.4.3.3 3D Integration 145
5.4.4 Thermal Management 146
5.4.5 Optical Coupling Solutions 146
5.5 Optical Alignment 147
5.5.1 Active vs Passive Alignment 147
5.5.2 Coupling Efficiency 148
5.6 Manufacturing Challenges 148
6 OPTICAL INTERCONNECT ARCHITECTURES FOR AI: PLUGGABLES, LPO/LRO, NPO AND CPO 151
6.1 The Rise and Challenges of Large Language Models (LLMs) 151
6.1.1 The Explosive Growth of AI and Generative AI 151
6.1.1.1 Historical Context and Acceleration 151
6.1.1.2 Compute Demand Scaling 151
6.1.1.3 Generative AI Market Expansion 151
6.1.2 Modern High-Performance AI Data Centre Requirements 154
6.1.2.1 Compute Density Requirements 154
6.1.2.2 Network Topology Requirements 154
6.1.2.3 Availability and Reliability Requirements 154
6.1.3 NVIDIA’s State-of-the-Art AI Systems 155
6.1.3.1 DGX H100 and HGX H100 155
6.1.3.2 Blackwell and Rubin Architectures 156
6.1.4 Switches: Key Components in Modern Data Centres 157
6.1.4.1 Switch Hierarchy in AI Data Centres 157
6.2 Scale-Up, Scale-Out, and Scale-Across Networks 159
6.2.1 Scale-Up Networks: GPU-to-GPU Interconnects 159
6.2.1.1 NVIDIA NVLink Implementation 159
6.2.2 Scale-Out Networks: Rack-to-Rack Communications 160
6.2.2.1 Ethernet-Based Scale-Out 160
6.2.2.2 InfiniBand for AI 161
6.2.2.3 CPO Value Proposition for Scale-Out 161
6.2.3 Scale-Up, Scale-Out, and Scale-Across Comparison 162
6.2.4 Roadmap of Interconnect Technology for Network Switches in High-End Data Centres 163
6.2.4.1 Technology Generations 163
6.2.5 SerDes Bottleneck in High-Bandwidth Systems 165
6.2.5.1 SerDes Function 165
6.2.5.2 Channel Loss Challenges 166
6.2.6 Solutions to SerDes Bottlenecks in High-Bandwidth Systems 166
6.2.6.1 Linear-Drive Electronics 166
6.2.6.2 Near-Package Optics 166
6.2.6.3 Co-Packaged Optics 167
6.2.7 Pluggable Optics: Current Bottlenecks and Limitations 167
6.2.7.1 Form Factor Constraints 167
6.2.7.2 Electrical Interface Limitations 167
6.2.8 On-Board Optics (OBO) 168
6.2.8.1 CPO Architecture 170
6.2.8.2 Key Enabling Technologies 170
6.2.8.3 Performance Benefits 171
6.2.8.4 Implementation Challenges 171
6.2.9 Transmission Losses in Pluggable Optical Transceiver Connections 171
6.2.10 Pluggable Optics vs. CPO 172
6.2.11 Design Decisions for CPO Compared to Pluggables 173
6.2.12 Advancements in Switch IC Bandwidth and the Need for CPO Technology 174
6.2.12.1 Bandwidth Scaling Trajectory 174
6.2.13 L2 Frontside Network Architecture Diagram: CPO vs. Non-CPO 176
6.3 Challenges in Compute Switch Interconnects (Optical I/O) for High-End Data Centres 178
6.3.1 Number of Copper Wires in Current AI System Interconnects 178
6.3.1.1 NVLink Copper Cable Count 178
6.3.2 Limitations of Current Copper Systems in AI 180
6.3.3 NVIDIA’s Connectivity Choices: Copper vs. Optical for High-Bandwidth Systems 181
6.3.3.1 Current Generation: Copper-Centric 181
6.3.3.2 Future Generation: Optical-First 181
6.3.4 Strategic Implications 182
6.3.5 Copper vs. Optical for High-Bandwidth Systems: Benchmark 182
6.3.6 Migration from Copper to Optical Interconnects for High-End AI Systems 182
6.3.7 Current AI System Architecture 185
6.3.8 L1 Backside Compute Architecture with Copper Systems 186
6.3.9 L1 Backside Compute Architecture with Optical Interconnect: Co-Packaged Optics (CPO) 186
6.4 Future AI Systems in High-End Data Centres 188
6.4.1 Power Efficiency Comparison: CPO vs. Pluggable Optics vs. Copper Interconnects 188
6.4.1.1 Power Consumption Breakdown 188
6.4.2 Latency of 60cm Data Transmission Technology Benchmark 190
6.4.3 Future AI Architecture (Short to Mid-Term) 190
6.4.4 Future AI Architecture (Long-Term) 193
7 CO-PACKAGED OPTICS (CPO) 197
7.1 Photonic Integrated Circuits (PICs) Key Concepts 197
7.1.1 What are Photonic Integrated Circuits (PICs)? 197
7.1.1.1 Fundamental Definition 197
7.1.1.2 Material Platforms 197
7.1.1.3 Integration Levels 197
7.1.2 PICs vs. Silicon Photonics: What are the Differences? 199
7.1.2.1 Silicon Photonics: A Specific Implementation 199
7.1.2.2 Why Silicon Photonics Dominates CPO 199
7.1.3 PIC Architecture 201
7.1.3.1 Transmit Path Architecture 201
7.1.3.2 Receive Path Architecture 201
7.1.3.3 Supporting Functions 202
7.1.3.4 Advantages and Challenges of PICs 202
7.2 Optical Engine (OE) 204
7.2.1 What is an Optical Engine? 204
7.2.1.1 Optical Engine Composition 204
7.2.1.2 Optical Engine vs. Pluggable Transceiver 204
7.2.2 How an Optical Engine Works 205
7.2.2.1 Transmit Path Operation 205
7.2.2.2 Receive Path Operation 205
7.2.2.3 Critical Performance Parameters 206
7.2.3 Optical Power Supplies 206
7.2.3.1 Why External Laser Sources? 206
7.2.3.2 External Laser Source Architectures 207
7.2.3.3 Optical Power Delivery 207
7.3 Three Key Concepts in Co-Packaged Optics (CPO) 207
7.3.1 Concept 1: Proximity Integration 207
7.3.2 Concept 2: Functional Partitioning 208
7.3.3 Concept 3: Coherent Ecosystem Development 208
7.3.4 Key Technology Building Blocks for CPO 209
7.3.4.1 Silicon Photonics PIC 209
7.3.4.2 Electronic IC (EIC) 210
7.3.4.3 EIC-PIC Integration 210
7.3.4.4 Fibre Array Units (FAUs) 210
7.3.4.5 External Laser Source 210
7.3.4.6 Advanced Packaging Platform 210
7.3.5 Benefits of CPO: Latency Reduction 213
7.3.5.1 Sources of Latency in Optical Interconnects 213
7.3.5.2 CPO Latency Advantages 213
7.3.6 Benefits of CPO: Power Consumption Reduction 214
7.3.6.1 Power Consumption Breakdown 214
7.3.6.2 Why CPO Consumes Less Power 214
7.3.7 Benefits of CPO: Data Rate Improvements 216
7.3.7.1 Pluggable Scaling Limitations 216
7.3.7.2 CPO Scaling Advantages 216
7.3.7.3 Data Rate Scaling Roadmap 216
7.3.7.4 The 200G-per-Lane Transition and Silicon Photonics 217
7.3.7.5 Modulator Technology Roadmap and Emerging Materials 217
7.3.7.6 Technology Trends in CPO Driven by Rising Data Rates 217
7.3.7.7 Applicability of Wavelength-Division Multiplexing (WDM) 219
7.3.7.8 Physical Limits on Fibre Count: The Beachfront (Shoreline) Constraint 220
7.3.7.9 Increasing the Number of WDM Channels: Technical Challenges 220
7.3.7.10 The End-to-End Optical Link Budget 221
7.3.8 Overview of Value Proposition of CPO 222
7.3.8.1 Value for Hyperscale Data Centre Operators 222
7.3.8.2 Value for Network Equipment Vendors 222
7.3.8.3 Value for the Technology Ecosystem 222
7.3.9 Future Challenges in CPO 223
7.3.9.1 Manufacturing and Yield Challenges 223
7.3.9.2 Thermal Management Challenges 223
7.3.9.3 Serviceability and Reliability Challenges 223
7.3.9.4 Ecosystem and Standardisation Challenges 224
7.3.9.5 Cost Challenges 224
7.3.9.6 Test and Manufacturing Scale-Up 224
7.4 CPO Standards 225
7.4.1 OIF Co-Packaging Framework 226
7.4.2 OCI-MSA (Optical Compute Interconnect Multi-Source Agreement) 227
7.4.3 OIF Standards for 1.6T and 3.2T CPO Module 227
7.4.4 External Laser Small Form Pluggable (ELSFP) Implementation Agreement 228
7.4.5 Telemetry and Management 229
7.4.6 OIF’s CEI-112G XSR / XSR+ PAM4 229
7.4.7 UCIe Standard and Its Relationship to CPO 230
7.4.8 XPO and Open CPX Initiatives 232
7.4.9 Near-Package Optics (NPO) as an Intermediate Path 232
8 CO-PACKAGED OPTICS MARKET ANALYSIS 233
8.1 CPO Market Definition and Scope 233
8.2 CPO Market Size and Growth Projections 233
8.3 Switch CPO Market Analysis 234
8.3.1 Market Overview and Drivers 234
8.3.2 Deployment Timeline and Adoption Phases 234
8.3.3 Volume Projections and Market Sizing 235
8.3.4 Market Concentration and Regional Distribution 236
8.3.5 Pricing Trajectory and Cost Dynamics 236
8.4 XPU Optical I/O Market Analysis 237
8.4.1 Market Drivers and Value Proposition 237
8.4.2 Adoption Timeline and Platform Evolution 237
8.4.3 Volume and Revenue Projections 238
8.4.4 Market Segmentation by Platform 239
8.4.5 Technology Requirements and Differentiation 239
8.5 CPO Pricing and Cost Analysis 240
8.5.1 Current Pricing Landscape 240
8.5.2 Cost Trajectory and Reduction Drivers 240
8.5.3 Cost Parity Timeline and Dynamics 241
8.5.4 Pricing Strategy Implications 242
8.6 Regional Market Dynamics 243
8.6.1 North America 243
8.6.2 Asia-Pacific 244
8.6.3 Europe 245
8.6.4 Rest of World 246
8.7 Total Addressable Market Analysis 247
8.7.1 Core TAM Segments 247
8.7.2 Serviceable Addressable Market (SAM) 248
8.8 Market Forecast by Component 249
8.9 Market Forecast by Technology Generation 250
8.9.1 Optical Engine Bandwidth Evolution 250
8.9.2 Generation Lifecycle Analysis 251
8.10 Market Restraints and Barriers 252
8.10.1 Manufacturing Yield and Cost 252
8.10.2 Serviceability and Field Replacement Concerns 253
8.10.3 Standards Maturity and Interoperability 253
8.10.4 Supply Chain Capacity Constraints 254
8.10.5 Competitive Alternatives 255
8.11 Adoption Curve Analysis 256
8.11.1 Technology Adoption Framework 256
8.11.1.1 Innovators (2024-2026) 256
8.11.1.2 Early Adopters (2026-2028) 257
8.11.1.3 Early Majority (2028-2031) 258
8.11.1.4 Laggards (2034+) 259
8.11.2 Segment-Specific Adoption Curves 260
8.12 Adoption Accelerators and Inhibitors 261
8.12.1 Adoption Curve Implications 261
8.13 Competitive Landscape Evolution 262
8.13.1 Current Competitive Positioning 262
8.13.2 Integrated Device Manufacturers (IDMs) 262
8.13.3 Silicon Photonics Specialists 262
8.13.4 Foundry/OSAT Providers 262
8.13.5 System Vendors 263
8.13.6 Laser Suppliers 263
8.13.7 Competitive Dynamics and Market Structure Evolution 264
8.13.7.1 Near-Term Dynamics (2025-2028) 264
8.13.7.2 Expected Evolution (2028) 264
8.13.7.3 Mid-Term Dynamics (2028-2032) 264
8.13.7.3.1 Expected Evolution (2032) 265
8.13.7.4 Long-Term Dynamics (2032-2037) 265
8.13.7.4.1 Expected Evolution (2037) 265
8.13.8 Vertical Integration Trends 266
8.13.8.1 Integration Strategy Framework 266
8.13.8.1.1 Full Vertical Integration 266
8.13.8.1.2 Partial Integration 266
8.13.8.1.3 Fabless/Assembly-Light 267
8.13.8.1.4 Platform Provider 267
8.13.8.2 Strategic Implications of Integration Trends 269
8.13.9 Recent Developments — Q1 2026 269
8.13.10 Recent Developments — Q2 2026 270
8.14 Scenario Analysis 271
8.14.1 Scenario Framework 271
8.14.2 Scenario Definitions 271
8.14.3 Bull Case Scenario 272
8.14.4 Base Case Scenario 272
8.14.5 Bear Case Scenario 273
8.14.6 Optical transceiver market 274
8.14.7 Scenario Comparison and Key Variables 274
9 GLOBAL MARKET SIZE AND FORECASTS 2027–2037 276
9.1 Headline Market Model 2027–2037 276
9.2 Market Segmentation by Application 2027–2037 276
9.3 Market Segmentation by Interconnect Architecture 2027–2037 277
9.4 Modules and PIC Dies 2027–2037 277
9.4.1 Global Silicon Photonics and Photonic Integrated Circuits Market Overview 278
9.4.1.1 Market Size and Growth Trends 278
9.4.1.2 Market Segmentation by Application 278
9.4.1.3 Server Boards, CPUs and Accelerators 279
9.4.1.4 Modules & PICs (Dies) Market Forecast 2027–2037 279
9.4.1.5 SOI Wafers for Silicon Photonics 280
9.4.1.6 LPO & New Modulator Materials Market Forecast 2027–2037 280
9.4.2 Datacom Applications 281
9.4.2.1 Market Forecast 281
9.4.2.1.1 Datacom and Telecom Modules and PICs 281
9.4.2.1.2 PIC Transceivers for AI 282
9.4.2.1.3 PIC Transceiver Pricing 282
9.4.2.2 PIC Transceiver Cost per Gigabit 283
9.4.2.3 PIC Datacom Transceiver Market 283
9.4.2.4 Datacom Transceiver Revenue by Customer Type 284
9.5 Quantum PIC Market 284
9.5.1. Key Drivers and Restraints 285
9.5.2 Co-Packaged Optics 285
9.5.3 Telecom Applications 286
9.5.3.1 Market Forecast 286
9.5.3.1.1 PIC-based Transceivers for 5G and 6G 286
9.5.3.2 Key Drivers and Restraints 287
9.5.4 Sensing Applications 287
9.5.4.1 Market Forecast 287
9.5.4.2 Key Drivers and Restraints 288
9.5.5 Photonic Integrated Circuit Market, by Material 289
10 SUPPLY CHAIN, TECHNOLOGY TRENDS AND FUTURE CHALLENGES 290
10.1 SUPPLY CHAIN ANALYSIS 290
10.1.1 Foundries and Wafer Suppliers 291
10.1.1.1 CMOS Foundries 291
10.1.1.2 Specialty Photonics Foundries 292
10.1.1.3 Indium Phosphide Wafer Supply 293
10.1.2 Integrated Device Manufacturers (IDMs) 294
10.1.2.1 Fabless Companies 294
10.1.2.2 Fully Integrated Photonics Companies 295
10.1.3 Foundries and Wafer Suppliers 296
10.1.4 Packaging and Testing 297
10.1.4.1 Chip-Scale Packaging 297
10.1.4.2 Module-Level Packaging 297
10.1.4.3 Testing and Characterization 297
10.1.4.4 Optical Module Assembly: The Shift to Southeast Asia 298
10.1.4.5 The EML Laser Shortage 298
10.1.5 System Integrators and End-Users 299
10.1.5.1 CPO Partner Ecosystems: NVIDIA and Broadco 300
10.2 TECHNOLOGY TRENDS 301
10.2.1 Laser Integration Techniques 301
10.2.1.1 Direct Epitaxial Growth 301
10.2.1.2 Flip-Chip Bonding 302
10.2.1.3 Hybrid Integration 302
10.2.1.4 Advances and Challenges 303
10.2.2 Modulator Technologies 304
10.2.2.1 Silicon Modulators 304
10.2.2.2 Germanium Modulators 305
10.2.2.3 Lithium Niobate Modulators 305
10.2.2.4 Polymer Modulators 305
10.2.2.4.1 Tower Semiconductor and Lightwave Logic EO-Polymer 306
10.2.3 Photodetector Technologies 306
10.2.3.1 Silicon Photodetectors 306
10.2.3.2 Germanium Photodetectors 307
10.2.3.3 III-V Photodetectors 307
10.2.4 Waveguide and Coupling Innovations 307
10.2.4.1 Silicon Waveguides 307
10.2.4.2 Silicon Nitride Waveguides 308
10.2.4.3 Coupling Techniques 308
10.2.5 Packaging and Integration Advancements 308
10.2.5.1 Chip-Scale Packaging 308
10.2.6 Wafer-Scale Integration 309
10.2.6.1 3D Integration and Interposer Technologies 309
10.3 CHALLENGES AND FUTURE TRENDS 310
10.3.1 CMOS-Foundry-Compatible Devices and Integration 310
10.3.1.1 Scaling and Miniaturization 311
10.3.1.2 Process Complexity and Yield Improvement 311
10.3.1.3 Energy-Efficient Photonic Devices 313
10.3.1.4 Thermal Optimization Techniques 313
10.3.2 Packaging and Testing 314
10.3.2.1 Advanced Packaging Solutions 314
10.3.2.2 Automated Testing and Characterization 315
10.3.3 Scalability and Cost-Effectiveness 315
10.3.3.1 Wafer-Scale Integration 316
10.3.3.2 Outsourced Semiconductor Assembly and Test (OSAT) 317
10.3.4 Emerging Materials and Hybrid Integration 317
10.3.4.1 Novel Semiconductor Materials 318
10.3.4.2 Heterogeneous Integration Approaches 318
10.3.5 Technology Readiness Assessment 319
11 COMPANY PROFILES 322 (160 company profiles)
12 REFERENCES 491
圖表清單 List of Tables & Figures
List of Tables
Table 1. Photonic Integrated Circuits Applications 36
Table 2. Silicon Photonics vs. Electronics: Key Metrics Comparison. 39
Table 3. Photonic Technologies Comparative Analysis. 44
Table 4. Comparison between electronic and photonic computing. 48
Table 5. Silicon Photonics technical achievements. 49
Table 6. Electronics companies silicon photonics commercial activities. 50
Table 7. Manufacturing Metrics & Challenges. 51
Table 8. Manufacturing Targets vs Current State. 52
Table 9. Regional Strengths & Research Focus. 55
Table 10. Comparative cost analysis. 57
Table 11. Challenges for CMOS-Foundry-Compatible Photonic Devices. 57
Table 12. Silicon Photonics Integration Schemes. 59
Table 13. Benefits of PICs. 60
Table 14. Current & Future Photonic Integrated Circuits Applications. 61
Table 15. Photodetector Performance. 63
Table 16. III-V Device Performance. 64
Table 17. Optical Modulator Performance Comparison. 65
Table 18. Silicon Photonic Waveguide Characteristics. 67
Table 19. Optical Component Integration Metrics. 68
Table 20. Advantages of Silicon Photonics. 69
Table 21. Applications of Silicon Photonics. 69
Table 22. Comparison with Other Photonic Integration Technologies. 70
Table 23. Silicon Photonics vs Traditional Electronics: Performance Metrics. 72
Table 24. Switch IC Bandwidth and CPO Technology Evolution. 74
Table 25. Challenges in data center architectures. 75
Table 26. Key Trends of Optical Transceivers in High-End Data Centers. 75
Table 27. Core Components Specifications and Requirements 76
Table 28. Types of Emission and Photon Sources/Lasers. 77
Table 29. III-V Integration Challenges. 78
Table 30. Laser Integration Approaches Comparison. 78
Table 31. Modulator Types and Configurations. 79
Table 32. Waveguide Specifications and Requirements. 81
Table 33. Optical Component Density Evolution. 82
Table 34. Data Transmission Parameters and Specifications. 83
Table 35. Circuit Architecture Building Blocks. 84
Table 36. Integration Approaches. 84
Table 37. Technology Platforms. 85
Table 38. Silicon Photonics Component Specifications. 86
Table 39. Optical Properties of Silicon. 86
Table 40. Fabrication Processes for Silicon Photonics. 87
Table 41. Silicon Semiconductor Foundry In-House Technologies. 88
Table 42. SOI Platform Benchmarking. 89
Table 43. Silicon Foundry Technology Comparison. 92
Table 44. Silicon-on-insulator (SOI) Platform Benchmarking. 93
Table 45. Key SOI Players. 94
Table 46. Germanium Integration Methods and Applications. 95
Table 47. SiN Key Foundries. 98
Table 48. SiN Modulator Technologies. 99
Table 49. Silicon (SOI and SiN) Device Heterogeneous Integration. 99
Table 50. SiN Benchmarking. 101
Table 51. Applications of SiN in Photonics. 102
Table 52. SiN PIC Players. 103
Table 53. SiN Foundry Analysis. 105
Table 54. Benchmarking of TFLN. 109
Table 55. Characteristics and Properties of LNOI. 110
Table 56. LNOI Fabrication Processes. 110
Table 57. LNOI-based Modulator and Switch Technologies. 111
Table 58. Emerging LNOI Device Technologies. 113
Table 59. InP Benchmarking. 114
Table 60. Integration Technologies. 115
Table 61. InP PIC Players. 115
Table 62. BTO Benchmarking. 117
Table 63. Comparative analysis of materials. 117
Table 64. Benchmarking of Polymer on Insulator. 118
Table 65. Wafer Size Comparison by Platform. 119
Table 66. Wafer Processing Challenges. 120
Table 67. Yield Analysis by Process Step. 120
Table 68. Integration Scheme Comparison. 121
Table 69. Bonding and Die-Attachment Techniques. 123
Table 70. Monolithic versus Hybrid Integration. 123
Table 71. Packaging Technology Comparison Matrix. 125
Table 72. Evolution of semiconductor packaging. 125
Table 73. Advanced Packaging Roadmap. 129
Table 74. Summary of key advanced semiconductor packaging approaches. 130
Table 75. Key Performance Metrics for Advanced Packaging Technologies. 131
Table 76. Glass Interposer Solutions. 134
Table 77. Organic Substrate Options. 135
Table 78. 3D Integration Approaches 135
Table 79. TSV Specifications by Application. 136
Table 80. TSV Challenges and Solutions. 138
Table 81. Comparative benchmark overview table of key semiconductor interconnection technologies 139
Table 82. CPO Benefits and Challenges. 141
Table 83. Performance Metrics Comparison. 142
Table 84. CPO Integration Approaches Comparison. 143
Table 85. Manufacturing Process Comparison. 144
Table 86. Thermal Management Approaches. 145
Table 87. Optical Coupling Solutions. 146
Table 88. Alignment Tolerance Analysis. 146
Table 89. Active vs Passive Alignment Comparison. 147
Table 90. Coupling Efficiency Analysis. 147
Table 91. Advanced packaging manufacturing challenges. 147
Table 92. AI Model Parameter and Compute Growth (2018-2030) 151
Table 93. Global AI Training Compute Demand Growth 152
Table 94. AI Data Centre Requirements by Workload Type 154
Table 95. Switch Hierarchy in AI Data Centres 157
Table 96. Scale-Up vs. Scale-Out vs. Scale-Across Comparison Matrix 161
Table 97. Interconnect Technology Roadmap (2020-2036) 163
Table 98. SerDes Bandwidth Limitations and Power Consumption 165
Table 99. SerDes Bottleneck Solutions Comparison 166
Table 100. Pluggable Optics Architecture and Limitations 167
Table 101. Signal Loss Comparison: Pluggable vs. CPO (dB) 171
Table 102. Comprehensive Pluggable vs. CPO Comparison 172
Table 103. Design Decision Framework for CPO Adoption 173
Table 104. Switch ASIC Bandwidth Scaling (51.2T → 102.4T → 204.8T) 174
Table 105. L2 Network Architecture Comparison 176
Table 106. Copper Wire Count in Current AI Systems 178
Table 107. Copper Interconnect Specifications by System 178
Table 108. Copper System Limitations Summary 180
Table 109. Copper vs. Optical Performance Benchmark 181
Table 110. Copper-to-Optical Migration Roadmap 182
Table 111. Power Consumption by Interconnect Technology 188
Table 112. Power Consumption Component Breakdown: Pluggable vs. CPO (400G) 188
Table 113. Latency Benchmark Comparison 189
Table 114. AI Architecture Evolution (2026-2030) 190
Table 115. PIC Component Overview 197
Table 116. PICs vs. Silicon Photonics Comparison 198
Table 117. Silicon Photonics vs. Other PIC Platforms: Capability Comparison 199
Table 118. PIC Advantages and Challenges Summary 202
Table 119. Optical Engine vs. Pluggable Transceiver Comparison 203
Table 120. External Laser Source Configurations 206
Table 121. CPO Technology Building Blocks 210
Table 122. CPO Technology Components and Suppliers 211
Table 123. Latency Comparison: Pluggable vs. CPO 213
Table 124. Power Consumption Comparison (pJ/bit Roadmap) 214
Table 125. Data Rate Scaling: Pluggable vs. CPO 215
Table 126. Emerging modulator technologies for CPO and high-speed optics 216
Table 127. Data-Rate Scaling Levers, Physical Ceilings, and Industry Responses 217
Table 128. WDM Variants for Co-Packaged Optics 218
Table 129. Representative Multi-Wavelength Source and Platform Demonstrations (2025–2026) 218
Table 130. Shoreline (Beachfront) Bandwidth Density 219
Table 131. Challenges of Higher WDM Channel Count and Mitigations 220
Table 132. Representative CPO Optical Link Budget (per channel, ELSFP output to receiver) 220
Table 133. CPO Value Proposition Summary 222
Table 134. CPO Technical Challenges and Mitigation Approaches 223
Table 135. CPO test scale-up: challenges and mitigations 224
Table 136. OIF CPO Standards Development Timeline 224
Table 137. OIF CPO Framework Functional Partitioning 225
Table 138. OIF CPO Module Specifications by Generation 226
Table 139. ELSFP Implementation Agreement Key Specifications 227
Table 140. CPO Telemetry and Management Requirements 228
Table 141. OIF CEI Specifications for CPO Applications 229
Table 142. UCIe Specifications and CPO Relationship 229
Table 143. China CPO Standards Landscape 230
Table 144. Pluggable vs. co-packaged optics: cost and serviceability 231
Table 145. Global CPO Market Forecast ($ Millions) 232
Table 146. Switch CPO Unit Volume Forecast (Thousands of Optical Engines) 234
Table 147. Switch CPO Market Forecast by Switch Generation ($M) 234
Table 148. CPO Cost Trajectory Projection 235
Table 149. XPU Optical I/O Market Forecast 237
Table 150. XPU Optical I/O Market Forecast by Platform ($M) 238
Table 151. CPO Cost Trajectory Projection 239
Table 152. CPO vs. Pluggable Cost Comparison (Per 800G Equivalent) 241
Table 153. Total Cost of Ownership Comparison (Per 51.2T Switch, 5-Year Lifetime) 241
Table 154. North America CPO Market Forecast 2026-2037 242
Table 155. Asia-Pacific CPO Market Forecast 2026-2037 243
Table 156. Europe CPO Market Forecast 2026-2037 244
Table 157. Rest of World CPO Market Forecast 2026-2037 245
Table 158. Global CPO Market Summary 246
Table 159. CPO Total Addressable Market Quantification 247
Table 160. CPO Serviceable Addressable Market 247
Table 161. CPO Component Market Forecast ($M) 248
Table 162. CPO Market by Optical Engine Generation ($M) 249
Table 163. CPO Commercial Milestones and Representative Products by Period 249
Table 164. Generation Share Evolution 250
Table 165. Manufacturing Yield Improvement Trajectory 252
Table 166. CPO Standards Development Timeline 253
Table 167. Market Restraints Summary 255
Table 168. CPO Adoption Curve by Segment (Penetration of Addressable Market) 259
Table 169. CPO Market Share by Participant (2024-2026) 262
Table 170. Near-Term Competitive Evolution 263
Table 171. Competitive Landscape Evolution Timeline 264
Table 172. Vertical Integration Trends by Participant Type 267
Table 173. Vertical Integration by Company 267
Table 174. Bull Case Market Forecast ($M) 271
Table 175. Base Case Market Forecast ($M) 271
Table 176. Bear Case Market Forecast ($M) 272
Table 177. Global optical transceiver market context (USD billion) 273
Table 178. Scenario Comparison Summary 273
Table 179. Global Silicon Photonics, LPO/LRO and NPO/CPO Market, 2027–2037 (US$ billion) 275
Table 180. Market Segmentation by Application, 2027–2037 (US$ billion) 275
Table 181. Optical-Interconnect Market by Architecture, 2027–2037 (US$ billion) 276
Table 182. Modules and PIC Dies Market Forecast, 2027–2037 (US$ billion) 276
Table 183. Global Silicon Photonics and PIC Market, 2027–2037 (US$ billion) 277
Table 184. Market Segmentation by Application 2027–2037 (Billions USD). 278
Table 185. Silicon Photonics on Server Boards, CPUs and Accelerators, 2027–2037 278
Table 186. Modules and PICs (Dies) Market Forecast, 2027–2037 (US$ billion) 279
Table 187. SOI Wafers for Silicon Photonics Market Forecast, 2027–2037 279
Table 188. LPO and New Modulator Materials Market Forecast, 2027–2037 (US$ billion) 280
Table 189. Silicon Photonics in Datacom Applications, 2027–2037 (US$ billion) 280
Table 190. Datacom and Telecom Modules Market Forecast, 2027–2037 (US$ billion) 280
Table 191. Datacom and Telecom PICs (Dies) Market Forecast, 2027–2037 (US$ billion) 281
Table 192. PIC Transceivers for AI, Units Forecast, 2027–2037 281
Table 193. PIC Transceiver Pricing, 2027–2037 (US$ per unit) 282
Table 194. PIC Transceiver Cost per Gigabit, 2027–2037 (US$ per Gb/s) 282
Table 195. PIC Datacom Transceiver Market Forecast, 2027–2037 282
Table 196. PIC Datacom Transceiver Revenue by Customer Type, 2027–2037 (US$ billion) 283
Table 197. Quantum PIC Market Forecast, 2027–2037 (US$ million) 283
Table 198. Key market drivers and restraints for silicon photonics in Datacom Applications. 284
Table 199. Co-Packaged Optics Market Forecast, 2027–2037 (US$ million) 284
Table 200. Silicon Photonics in Telecom Applications, 2027–2037 (US$ billion) 285
Table 201. PIC-based Transceivers for 5G and 6G, Units and Market, 2027–2037 285
Table 202. Key market drivers and restraints for silicon photonics in Telecom Applications. 286
Table 203. Silicon Photonics in Sensing Applications, 2027–2037 (US$ billion) 286
Table 204. Key market drivers and restraints for silicon photonics in Sensing Applications. 287
Table 205. PIC Market by Material Platform, 2027–2037 (US$ billion) 288
Table 206. Silicon Photonics Supply Chain and Ecosystem. 289
Table 207. CMOS Foundries. 290
Table 208. Specialty Photonics Foundries. 291
Table 209. Fabless Companies. 293
Table 210. Fully Integrated Photonics Companies. 294
Table 211. Foundries and Wafer Suppliers. 295
Table 212. System Integrators and End-Users. 298
Table 213. Laser Integration Methods Comparison. 300
Table 214. Advanced Techniques and Challenges. 302
Table 215. Modulator Technology Benchmarking. 303
Table 216. Photodetector Performance Metrics . 305
Table 217. Novel semiconductor materials for silicon photonics. 317
Table 218. Technology readiness of silicon photonics technologies, 2026 319
List of Figures
Figure 1. Silicon Photonic Transceiver Evolution Timeline. 40
Figure 2. Silicon Photonics Player Market Map. 43
Figure 3. Basic Silicon Photonic Circuit Architecture. 56
Figure 4. High Performance AI data center. 74
Figure 5. Optical IO Coupling Mechanisms Diagram. 77
Figure 6. Optical Component Density Evolution. 82
Figure 7. Basic Optical Data Transmission Diagram. 83
Figure 8. SOI Wafer Structure. 88
Figure 9. Manufacturing Process Flow. 92
Figure 10. Germanium Photodetector. 96
Figure 11. Silicon Nitride Layer 97
Figure 12. SiN Waveguide Cross-sections. 101
Figure 13. LNOI Device Structures 110
Figure 14. Timeline of different packaging technologies. 127
Figure 15. Advanced Packaging Roadmap. 129
Figure 16. 2D chip packaging. 132
Figure 17. Typical structure of 2.5D IC package utilizing interposer. 134
Figure 18. TSV Structure and Implementation. 137
Figure 19. Hybrid Bonding Process Flow. 140
Figure 20.Co-Packaged Optics Architecture. 141
Figure 21. LLM Parameter Growth Timeline (GPT-1 to GPT-5 and Beyond) 152
Figure 22. DGX H100/H200 system topology 155
Figure 23. NVIDIA Rubin Architecture Overview 156
Figure 24. Scale-Up Network Topology (NVLink, NVSwitch) 159
Figure 25. Scale-Out and Scale-Up Network Topology (Ethernet/InfiniBand) 160
Figure 26. Three-Tier Network Architecture Diagram 162
Figure 27. Interconnect Technology Roadmap (2020-2036) 164
Figure 28. On-Board Optics Configuration 168
Figure 29. Switch ASIC Bandwidth Scaling (51.2T → 102.4T → 204.8T) 175
Figure 30.Copper-to-Optical Migration Roadmap 183
Figure 31.Current AI System Interconnect Architecture 184
Figure 32. AI Architecture Evolution (2026-2030) 191
Figure Figure 33. AI Architecture Vision (2031-2037) 195
Figure 34. PIC Architecture for CPO Applications 201
Figure 35. CPO Key Concepts Illustration 208
Figure 36. Power Consumption Comparison (pJ/bit Roadmap) 214
Figure 37. Silicon Photonics Supply Chain and Ecosystem. 290
Figure 38. NVIDIA's silicon photonics switches. 412
Figure 39. PhotoniSol optical isolator chip. 420
Figure 40. Q.ANT Native Processing Unit (NPU). 425
Figure 41. QuiX low-loss photonic quantum processors. 433
Figure 42. A prototype of Taara’s silicon photonics chip device. 486
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