報告摘要
The generative AI hardware materials market covers the materials and components used to build AI training and inference systems, from raw substrates and gases through to finished server racks. Demand is driven by hyperscaler, enterprise and sovereign capital expenditure on AI datacentres, and by the growing share of AI compute performed at the edge.
System performance is limited by a set of physical constraints rather than by model design. Compute throughput is limited by reticle area and transistor density. Memory bandwidth is limited by HBM stack height and pin width. Interconnect bandwidth is limited by signal attenuation in copper traces above roughly 224 Gbps per lane. Heat removal is limited by thermal interface conductivity and coolant flow rate. Power delivery is limited by IR drop and voltage regulator efficiency. Progress against each constraint depends on a specific materials or packaging development, which is why this layer determines how quickly AI compute capacity can be added.
The market is structured in nine layers: raw materials, gases and photoresists; power semiconductors and delivery; thermal materials and cooling; photonics packaging; substrates and interposers; advanced packaging; HBM and the memory subsystem; AI accelerator silicon; and AI servers and racks. A related but separate segment is the datacentre construction supply chain, covering power infrastructure, cooling plant, buildings and engineering services.
Growth rates differ substantially by layer. AI accelerator silicon is the largest segment but grows more slowly than several of the layers below it. HBM and advanced packaging gain share over the forecast period, as stack heights increase and CoWoS-class packaging capacity remains tight. Photonics packaging and datacentre power semiconductors grow fastest from a smaller base, as co-packaged optics moves into volume production and rack power levels rise above 300 kW. Cooling shifts away from air: direct liquid cooling and immersion account for more than 60% of new AI deployments by 2030.
Two structural characteristics are relevant to suppliers and buyers. The first is geographic concentration. Taiwan, South Korea and Japan account for most leading-edge silicon, memory, packaging, substrate and specialty materials capacity, and CoWoS-class packaging is the most constrained single step. The second is the effect of export controls, which have led to a separate hardware supply chain in China with its own suppliers and process node limits. The capability gap between the two is narrowing fastest in small-model inference and slowest in frontier model training.
Report contents include:
Executive summary — headline findings, the hardware bottleneck, value-chain map and implications by stakeholder
The compute stack — training and inference economics, cloud, edge and sovereign AI, and the cost weighting of memory and packaging
AI accelerator silicon — GPUs, hyperscaler ASICs, alternative architectures, the Chinese ecosystem, foundry roadmaps and wafer-level integration
AI-driven chip design (EDA) — incumbent vendor initiatives, the startup cohort and AI-EDA market forecasts
High bandwidth memory and beyond — HBM roadmap and capacity, custom HBM, compute-in-memory, CXL pooling and 3D DRAM
Advanced packaging and substrates — 2.5D and 3D integration, CoWoS capacity, ABF and FC-BGA substrates, interposers, hybrid bonding and OSAT capacity
Co-packaged optics and silicon photonics — CPO architecture, optical I/O chiplets, photonics foundries and packaging supply chain
Thermal management — thermal interface materials, vapour chambers, cold plates, immersion and microfluidic cooling
Power delivery and the GaN/SiC transition — 48V and 800V HVDC architectures, SiC and GaN device and substrate supply, VRMs, server PSUs and backside power delivery
Networking and optical materials — switch silicon, pluggable transceivers, DSP and SerDes, III-V materials, NICs, DPUs and connectors
Datacentre construction — power infrastructure including SMRs, facility cooling, modular designs and site selection
Edge GenAI hardware — AI smartphones and PCs, automotive silicon, robotics compute and edge accelerator start-ups
Regional analysis — Taiwan, South Korea, Japan, China, Southeast Asia, the United States, Europe and Israel
Supply chain and geopolitics — China's domestic supply chain, CHIPS Act implementation, critical materials and single-point-of-failure analysis
Sustainability and embodied carbon — operational emissions, fab embodied carbon, water use, renewable procurement and disclosure standards
Market forecasts and strategic outlook — segment, regional and customer-tier forecasts, choke-point analysis, M&A and investment framework
Appendix — methodology, definitions, abbreviations, sources and year-by-year forecast outputs
Companies profiled include 1X Technologies, 3M, Acbel Polytech, Accelink Technologies, Achronix Semiconductor, Advanced Micro Devices (AMD), AGC (Asahi Glass), Agility Robotics, AheadComputing, Ajinomoto FineTechno (ABF), Akhan Semiconductor, Alibaba THead (PingTouGe), Alpha Assembly Solutions (MacDermid Alpha), Alphabet Inc. (Google), Amazon Web Services (AWS), Ambarella, Amber Semiconductor (AmberSemi), AMD, Amkor Technology, Amphenol Corporation, Anduril Industries, Apple Inc., Applied Materials, Apptronik, Arago, ASE Group, ASE Technology Holding (incl. SPIL), Asetek, Asia Vital Components (AVC), ASMPT, Asperitas, Astera Labs, Astrus, AT&S (Austria Technologie & Systemtechnik), Auras Technology, Avalanche Technology, Axelera AI, Axera Technology, AXT Inc., Ayar Labs, BE Semiconductor Industries (BESI), Biren Technology, Black Sesame Technologies, Blaize, Broadcom Inc., Cambricon Technologies, Cambridge GaN Devices (CGD), Carbice Corporation, Celero Communications, Cerebras Systems, Chemours Company, ChipAgents, Chipmind, ChipMOS Technologies, Chiral, Ciena, Cisco Systems, Claros, Coherent Corp., ColorChip, Cooler Master Co., CoolIT Systems, CoreWeave Inc., Corintis, Corning Incorporated, Crossbar Inc., Crusoe Energy Systems, CXMT (ChangXin Memory Technologies), DEEPX, Delta Electronics, d-Matrix, DOW Inc., Dust Photonics, Eaton Corporation, EdgeCortix, EFFECT Photonics, Efficient Computer, Efficient Power Conversion (EPC), Element Six (e6), Eliyan, Empower Semiconductor, Engineered Fluids, Eoptolink Technology, Eridu, Etched.ai, Ethernovia, EuQlid, EV Group (EVG), Everspin Technologies, Fabric8Labs, Fabrinet, Femtum, Ferroelectric Memory Company (FMC), Figure AI, Fourier Intelligence, Foxconn Industrial Internet (FII), Foxconn Interconnect Technology (FIT), Frore Systems, FSP Group, Fujipoly, Furiosa AI, G42, Gaianixx, Galatek, Gigalight, Google, Great Sky, Green Revolution Cooling (GRC), GreenWaves Technologies, Groq Inc., GS Microelectronics (GSME), Hailo Technologies, Henkel AG, Heraeus, Hesheng Silicon Industry, Hisense Broadband, HiSilicon (Huawei), Hitachi Energy, Hon Hai (Foxconn), Honeywell International, Horizon Robotics, Hua Tian Technology (HT-Tech), Huawei Technologies, Huawei Technologies (HiSilicon), Hummink, Ibiden Co. Ltd., Iceotope Technologies, Iluvatar CoreX, Indium Corporation, Infineon Technologies AG, Innolight Technology, Innoscience Technology, Intel, Intel Corporation, Intel Foundry, IQE plc, JCET Group, JetCool Technologies, Kandou AI, Kaneka Corporation, Kinsus Interconnect Technology, Kioxia Holdings, Kneron, Kulicke & Soffa Industries (K&S), Kyocera Corporation and more
授權報價
| Single User | $1,200 GBP |
目錄 Table of Contents
1 EXECUTIVE SUMMARY 23
1.1 Key Findings 23
1.2 The Generative AI Hardware Bottleneck 23
1.3 Materials Value Chain at a Glance 24
1.4 Eleven-Year Forecast Highlights 25
1.5 Strategic Implications for Asian Foundries, OSAT, Memory, Substrate, and Cooling Vendors 27
1.6 Differentiation vs. Adjacent Coverage 29
1.7 Major Market Players 29
2 THE COMPUTE STACK BEHING GENERATIVE 31
2.1 Training vs. Inference Economics 31
2.1.1 Pre-training, post-training, RLHF compute splits 33
2.1.2 Inference token economics and serving infrastructure 33
2.1.3 Test-time compute and reasoning-model demand 35
2.2 Cloud, Edge, and Sovereign AI 35
2.2.1 Hyperscaler clusters at 100,000-GPU scale 35
2.2.2 Enterprise on-prem and neocloud deployments 35
2.2.3 Sovereign AI build-outs 35
2.2.4 Edge inference cross-reference 37
2.3 Why Memory Bandwidth and Packaging Dominate Cost 37
2.3.1 The memory wall in LLM serving 38
2.3.2 HBM ASP as percentage of AI accelerator BOM 39
2.3.3 CoWoS as the constraining bottleneck 40
2.4 Materials and Components as the New Bottleneck 40
2.5 Hyperscaler vs. Enterprise vs. Sovereign Capex 41
2.6 Company Profiles 43 (9 company profiles)
3 AI ACCELERTOR SILICON 53
3.1 GPUs 53
3.1.1 NVIDIA roadmap: Hopper → Blackwell → Blackwell Ultra → Rubin → Rubin Ultra 53
3.1.2 NVL72 rack architecture and post-Rubin scale-up 54
3.1.3 AMD MI300X → MI355X → MI400 trajectory 56
3.1.4 Intel Gaudi and the post-Gaudi roadmap 56
3.2 Custom Hyperscaler ASICs 56
3.2.1 Google TPU v5/v6/v7 and ML supercomputer architecture 58
3.2.2 AWS Trainium 2/3 and Inferentia 58
3.2.3 Microsoft Maia and Cobalt 58
3.2.4 Meta MTIA generations 58
3.2.5 ASIC NRE economics and break-even analysis 58
3.3 Domain-Specific and Challenger Architectures 59
3.3.1 Cerebras WSE-3 wafer-scale 61
3.3.2 Groq LPU deterministic inference 61
3.3.3 SambaNova RDU and dataflow 61
3.3.4 Tenstorrent, d-Matrix, Etched, Rivos, Lightmatter 61
3.4 Chinese AI Chip Ecosystem 62
3.4.1 Huawei Ascend 910C / 910D / 950 64
3.4.2 Cambricon, Biren, Moore Threads, Iluvatar CoreX 64
3.4.3 Alibaba T-Head Hanguang and PingTouGe 65
3.4.4 Domestic substitution timeline to gen-on-gen parity 65
3.5 Process Nodes and Foundry Roadmaps 66
3.5.1 TSMC: N3 → N3P → N2 → N2P → A16 → A14 68
3.5.2 Samsung Foundry: 3GAP → 2GAP → SF1.4 68
3.5.3 Intel Foundry: 18A → 14A and external customer pipeline 69
3.5.4 SMIC: N+1 / N+2 and the EUV-free 5nm question 69
3.5.5 EUV and High-NA EUV adoption curves 69
3.6 Wafer-Level Integration and Reticle Stitching 69
3.7 Company Profiles 70 (53 company profiles)
4 AI-DRIVEN CHIP DESIGN (EDA) 124
4.1 The EDA Bottleneck in the AI Hardware Era 124
4.2 The Recursive Loop: AI Designing AI Hardware 124
4.3 The Incumbent EDA Vendors' AI Initiatives 125
4.4 The Startup Cohort: Four Distinct Approaches 126
4.4.1 Agentic AI for digital design and verification 126
4.4.2 Physics-AI for simulation and advanced packaging 126
4.4.3 AI for analog and PCB design 127
4.4.4 EDA-adjacent silicon and applied AI 127
4.5 Geographic Distribution 127
4.6 Market Forecast: AI-EDA Tools 2026–2037 128
4.7 Strategic Implications 128
4.8 Company profiles 129 (6 company profiles)
5 HIGH BANDWIDTH MEMORY AND BEYOND 136
5.1 HBM Architecture and TSV Stacking Fundamentals 136
5.2 HBM Generation Roadmap 137
5.2.1 HBM3 / HBM3E specifications and deployment 138
5.2.2 HBM4 / HBM4E: pin width doubling and base-die logic 139
5.2.3 HBM5 / HBM5E: 2031–2037 architecture directions 139
5.3 Memory Makers and Capacity Outlook 140
5.3.1 SK hynix strategy, products, capex through 2030 141
5.3.2 Samsung HBM3E re-qualification and HBM4 catch-up 142
5.3.3 Micron HBM3E entry and AI customer share gains 143
5.3.4 HBM bit-shipment and wafer-capacity forecasts 144
5.4 Custom HBM (cHBM) and Base-Die Innovation 145
5.4.1 Customer-specific HBM with NVIDIA, Broadcom, Google 146
5.4.2 Standard vs custom HBM revenue split through 2030 147
5.5 Compute-in-Memory and Processing-in-Memory at Scale 147
5.6 Emerging Memory for AI Datacenters 149
5.6.1 Storage-class memory after 3D XPoint 150
5.7 Memory Pooling and CXL Fabrics 150
5.8 3D DRAM — The Post-2030 Path 152
5.9 Company Profiles 153 (23 company profiles)
6 ADVANCED PACKAGING AND SUBSTRATE MATERIALS 177
6.1 The 2.5D / 3D Architecture Continuum 177
6.2 TSMC CoWoS and the Capacity Constraint 179
6.2.1 CoWoS-S, CoWoS-L, CoWoS-R roadmap 180
6.2.2 CoWoS-Photonics and CoWoP 180
6.2.3 CoWoS capacity expansion: 2024 vs. 2026 vs. 2028 vs. 2030 180
6.2.4 SoIC, SoIC-X, SoIC-P: Hybrid-Bonded Stacks 181
6.3 Intel and Samsung Advanced Packaging 182
6.3.1 Intel: EMIB, EMIB-T, Foveros, Foveros Direct, Foveros Omni 182
6.3.2 Samsung: I-Cube, X-Cube, H-Cube 182
6.4 Substrate Technologies (ABF, FC-BGA) 183
6.4.1 ABF supply oligopoly 183
6.4.2 Glass core substrate (Intel, ASE, SCHOTT) 183
6.5 Interposer Materials (Silicon TSV, Glass, Organic RDL) 184
6.6 Hybrid Bonding and Copper-to-Copper Interconnect 185
6.6.1 Hybrid bonding equipment ecosystem 185
6.6.2 HBM4 adoption of hybrid bonding 185
6.7 OSAT Capacity and Asian Dominance 186
6.8 Advanced Packaging Materials Suppliers 187
6.9 Company Profiles 188 (56 company profiles)
7 CO-PACKAGED OPTICS AND SILICON PHOTONICS FOR AI 245
7.1 The Optical Interconnect Imperative 245
7.2 CPO Architecture and the Two Network Layers 246
7.3 TSMC COUPE, CoWoS-Photonics, iOIS 247
7.3.1 TSMC photonics design ecosystem 248
7.3.2 CoWoP and the NVIDIA Rubin transition 248
7.4 ASE VIPack and the Merchant Photonics Packaging Layer 248
7.5 Optical I/O Chiplets: AyarLabs, Lightmatter, Celestial AI 249
7.5.1 AyarLabs TeraPHY 249
7.5.2 Lightmatter Passage 249
7.5.3 Celestial AI Photonic Fabric and the Marvell acquisition 249
7.6 Switch Silicon and Co-Packaged Optical Engines 250
7.7 Silicon Photonics Foundries 250
7.8 Photonics Packaging Materials and Supply Chain 251
7.9 Market Sizing for Photonics Packaging 2026–2037 252
7.10 Company Profiles 253 (28 company profiles)
8 THERMAL MANAGEMENT FOR AI DATA CENTERS 282
8.1 The Thermal Crisis: Power Density at the Package Level 282
8.2 Thermal Interface Materials (TIMs) 283
8.2.1 Liquid metal TIM and the gallium corrosion problem 284
8.2.2 Solder TIM (indium and SnAg) 285
8.2.3 Diamond-based TIMs and emerging materials 285
8.3 Heat Spreaders, Vapor Chambers, and Heat Pipes 285
8.4 Cold Plates and Direct-to-Chip Liquid Cooling 286
8.4.1 Cold plate design and microchannel geometry 286
8.4.2 The cold plate supply chain bottleneck 287
8.5 Immersion Cooling 288
8.5.1 Single-phase immersion: mineral oil and synthetic dielectrics 288
8.5.2 Two-phase immersion: fluorocarbons and the PFAS challenge 289
8.6 Microfluidic and In-Package Cooling 290
8.6.1 Microfluidic ecosystem and the first commercial applications 291
8.6.2 Coolant Distribution Units, Manifolds, and Facility Plumbing 291
8.7 Market Forecast: AI-Tied Thermal Management 2024–2037 292
8.8 Company Profiles 292 (40 company profiles)
9 POWER DELIVERY AND GAN/SIC TRANSITION 333
9.1 The Power Crisis: From 12V to 48V to 800V HVDC 333
9.2 The Power Hierarchy: System → Board → Package → Die 334
9.2.1 48V tray architecture and the OCP standard 335
9.2.2 800V HVDC at the rack and the Rubin transition 335
9.3 SiC Devices and Substrate Supply 335
9.3.1 SiC substrate supply: the bottleneck 336
9.4 GaN Devices: Lateral, Vertical, Cascode 337
9.4.1 GaN switching speed and AI server PSU applications 338
9.4.2 Vertical GaN: the post-2027 trajectory 338
9.5 Voltage Regulator Modules and Multi-Phase Point-of-Load 339
9.5.1 The Monolithic Power Systems advantage in AI VRMs 340
9.5.2 Vertical power delivery and the package-integrated VRM 341
9.6 Server Power Supply Units and Rack Rectifier Shelves 341
9.7 Backside Power Delivery (BSPDN) 342
9.7.1 Intel PowerVia (18A) 342
9.7.2 TSMC backside power (A16) 342
9.7.3 Samsung BSPDN 342
9.8 Market Forecast: AI Datacenter Power Semiconductors 2024–2037 343
9.9 Company Profiles 343 (42 company profiles)
10 NETWORKING AND OPTICAL MATERIALS 386
10.1 The Three Network Layers in an AI Datacenter 386
10.2 Switch Silicon Roadmap 386
10.2.1 Tomahawk 6 Davisson and the CPO inflection 387
10.2.2 NVIDIA Spectrum-X and Quantum-X 387
10.2.3 Ultra Ethernet Consortium (UEC) 388
10.3 Pluggable Optical Transceivers 388
10.3.1 Volume optical transceiver suppliers 388
10.3.2 Optical transceiver assembly: Fabrinet, Jabil, Luxshare 389
10.4 DSP and SerDes for Optical Transceivers 389
10.4.1 Marvell's DSP business and the AI optical transceiver 390
10.4.2 Linear Pluggable Optics (LPO) and the DSP-less transceiver 390
10.5 III-V Materials Layer: InP, GaAs, GaN-Photonics 391
10.6 NICs, DPUs, and SmartNICs 391
10.7 Cables, Connectors, and Direct Attach Copper 392
10.8 Market Forecast: AI-Tied Networking and Optical 2024–2037 393
10.9 Company Profiles 394 (36 company profiles)
11 DATA CENTER CONSTRUCTION AND SUSTAINABILITY 431
11.1 The AI Datacenter Buildout: Scale and Scope 431
11.2 Power Infrastructure: Grid, On-Site Generation, and SMRs 432
11.2.1 Behind-the-meter natural-gas generation 432
11.2.2 Nuclear restart and Small Modular Reactor procurement 432
11.2.3 Renewable energy procurement at hyperscaler scale 433
11.2.4 Switchgear and transformers: the silent bottleneck 433
11.3 Facility-Level Cooling Architecture 435
11.4 Construction Supply Chain and Modular Datacenter Architecture 436
11.5 Geographic Concentration and Site Selection 438
11.5.1 The Top 12 AI Datacenter Regions (2026) 438
11.5.2 Climate as a constraint 439
11.6 PUE, WUE, and Sustainability Metrics 439
11.6.1 Carbon-Free Energy (CFE) accounting 439
11.6.2 Embodied carbon and circular economy 439
11.7 Regulatory Framework 440
11.7.1 Permit and interconnection timelines 440
11.8 Market Forecast: AI Datacenter Construction Supply Chain 2024–2037 440
12 EDGE GENAI HARDWARE 441
12.1 The Edge AI Taxonomy 441
12.2 AI Smartphones 442
12.2.1 Apple Neural Engine evolution 443
12.3 AI PCs 444
12.3.1 NVIDIA's AI PC entry 445
12.3.2 Snapdragon X Elite and Qualcomm's PC push 445
12.4 NVIDIA Jetson and the Embedded AI Platform 445
12.4.1 Jetson AGX Thor and humanoid robotics 446
12.5 Automotive AI Silicon 446
12.5.1 NVIDIA DRIVE Thor and the L4 autonomous driving platform 447
12.5.2 Tesla FSD and the captive silicon path 447
12.6 Humanoid Robotics: The Emerging Edge AI Compute Frontier 447
12.6.1 Humanoid robot unit volumes and silicon revenue forecast 448
12.7 Edge AI Accelerator Start-ups 448
12.8 Edge AI Memory: LPDDR5X, On-Chip SRAM, eMRAM 449
12.9 Market Forecast: Edge AI Silicon 2024–2037 449
12.10 Company Profiles 450 (51 company profiles)
13 REGIONAL ANALYSIS: GEOGRAPHY OF THE GENAI HARDWARE SUPPLY CHAIN 502
13.1 The Asian Concentration 502
13.2 Taiwan 503
13.2.1 The TSMC scale 503
13.2.2 The Taiwan supply chain depth 503
13.2.3 Taiwan's geographic concentration risk 503
13.3 South Korea 504
13.3.1 SK hynix as the strategic anchor 504
13.3.2 Samsung: vertical integration across the stack 504
13.3.3 Korean specialty positions 504
13.4 Japan 505
13.4.1 Kumamoto and the broader Japanese fab expansion 505
13.5 China 506
13.5.1 Chinese domestic AI silicon volume and trajectory 506
13.5.2 The SMIC constraint 506
13.5.3 China's strength layers 507
13.6 Southeast Asia and India 507
13.6.1 Malaysian AI infrastructure 507
13.6.2 India's emerging fab and OSAT capacity 508
13.6.3 ASEAN AI cloud and sovereign-AI initiatives 508
13.7 The United States 509
13.7.1 The CHIPS Act build-out 509
13.7.2 The US labour and supply chain constraints 509
13.8 Europe and Israel 510
13.8.1 ASML 510
13.8.2 European Chips Act and the limits of European industrial policy 510
13.8.3 Israel's specialty position 510
13.9 The Rest of World: Niche Capabilities and Sovereign Ambitions 511
13.10 Aggregate Regional Capture: Scenario Analysis 2026–2037 512
14 SUPPLY CHAIN AND GEOPOLITICS 513
14.1 The Defining Tensions 513
14.2 The China Strategy: Sovereign Stack and Domestic Substitution 513
14.2.1 SMIC's role and the EUV-free leading-edge path 514
14.2.2 The CXMT and JHICC HBM ramp 514
14.2.3 China's wafer-fab equipment indigenisation 514
14.3 US CHIPS Act Implementation and Domestic Reshoring 515
14.3.1 TSMC Arizona 515
14.3.2 Samsung Taylor 515
14.3.3 Intel Foundry 515
14.3.4 Micron's CHIPS-supported expansion 515
14.3.5 The labour and ecosystem constraints 516
14.4 European Chips Act and Strategic Autonomy 516
14.4.1 The European specialty position 516
14.5 The Critical Materials Layer 517
14.5.1 Rare earths 517
14.5.2 Gallium and germanium 517
14.5.3 Neon and specialty gases 517
14.5.4 Specialty quartz, silicon, and substrates 517
14.6 Single-Point-of-Failure Analysis 518
14.7 Scenarios for Supply Chain Resilience 519
14.7.1 The "successful diversification" scenario (Bull case for resilience) 519
14.7.2 The "concentrated capacity" scenario (Base case) 520
14.7.3 The "geopolitical disruption" scenario (Bear case for resilience) 520
14.8 Sovereign AI as a Strategic Demand Driver 520
15 SUSTAINABILITY AND EMBODIED CARBON 522
15.1 The Sustainability Stakes 522
15.2 Operational Emissions: Training, Inference, and the Cooling Energy Tax 522
15.2.1 Training versus inference: the dominant share 523
15.3 Embodied Carbon in Semiconductor Manufacturing 523
15.3.1 The PFC and process-gas problem 523
15.3.2 Embodied carbon at the device level 524
15.3.3 Server-level and facility-level embodied carbon 524
15.4 Water, Chemicals, and Resource Intensity 525
15.4.1 PFAS chemistry and the transition 525
15.5 Renewable Energy Procurement at Hyperscaler Scale 525
15.5.1 Nuclear restart and SMR as carbon-free baseload 526
15.5.2 On-site natural gas: the carbon offset 526
15.6 Heat Recovery, Circular Economy, and End-of-Life 527
15.6.1 Heat recovery and district heating 527
15.6.2 Circular economy and component reuse 527
15.7 Carbon Accounting Standards and Corporate Disclosure 528
15.7.1 Scope 1, 2, 3 framework 528
15.7.2 EU Corporate Sustainability Reporting Directive 528
15.7.3 SEC climate disclosure rules 528
15.7.4 Carbon pricing and offsets 528
15.8 Green Manufacturing Practices at Major Suppliers 529
15.8.1 Process gas abatement 529
15.8.2 Water recycling and reuse 529
15.9 Market and Regulatory Outlook 2026–2037 530
15.9.1 Carbon-related regulatory tightening 530
15.9.2 Embodied-carbon-conscious procurement 530
15.9.3 The carbon-aware AI compute frontier 530
16 MARKET FORECASTS: GENAI HARDWARE 2026-2037 531
16.1 Forecast Methodology and Framework 531
16.2 Total GenAI Hardware Market — Base Case Forecast 532
16.3 Bull/Base/Bear Scenarios at Aggregate Level 533
16.4 AI Accelerator Silicon Sub-Segment Forecast 534
16.4.1 Merchant vs. captive ASIC share trajectory 535
16.4.2 China sovereign-stack AI silicon trajectory 535
16.5 HBM and Memory Sub-Segment Forecast 535
16.6 Advanced Packaging Sub-Segment Forecast 536
16.7 Photonics Packaging Sub-Segment Forecast 536
16.8 Thermal Management Sub-Segment Forecast 537
16.9 Power Delivery Sub-Segment Forecast 537
16.10 Networking and Optical Sub-Segment Forecast 538
16.11 Datacenter Construction Supply Chain Sub-Segment Forecast 538
16.12 Edge AI Silicon Sub-Segment Forecast 539
16.13 Regional Capture Forecast 539
16.14 Customer Tier Forecast 540
16.15 Key Forecast Risks and Sensitivities 540
16.15.1 The CapEx normalisation risk 540
16.15.2 The Taiwan concentration risk 541
16.15.3 Model training economics 541
16.15.4 Chinese sovereign-stack acceleration 541
16.15.5 Power infrastructure constraints 541
17 STRATEGIC OUTLOOK 542
17.1 The Five Defining Themes of the GenAI Hardware Decade 542
17.2 The Choke-Point Map 543
17.3 The Strategic Investment Framework 544
17.4 M&A Landscape and Strategic Consolidation 545
17.4.1 Photonics consolidation 545
17.4.2 Memory and HBM consolidation 545
17.4.3 Equipment and tools consolidation 545
17.4.4 AI silicon start-up consolidation 546
17.4.5 Forward M&A trajectory through 2030 547
17.5 Sensitivity Analysis 547
17.6 Strategic Implications by Stakeholder 548
17.6.1 For AI accelerator silicon designers 548
17.6.2 For hyperscalers and AI cloud operators 548
17.6.3 For memory manufacturers 549
17.6.4 For foundries 549
17.6.5 For OSATs and substrate suppliers 549
17.6.6 For thermal and power infrastructure suppliers 549
17.6.7 For photonics packaging participants 549
17.6.8 For governments and policymakers 549
17.7 What Could Change This Forecast 550
17.7.1 Upside surprises 550
17.7.2 Downside surprises 550
17.7.3 Structural rather than cyclical risk 550
18 APPENDIX 552
18.1 Forecast Methodology 552
18.1.1 Unit volume forecast construction 552
18.1.2 ASP and content-per-unit forecast construction 552
18.1.3 Scenario construction 552
18.1.4 Cross-validation 553
18.2 Definitions and Terminology 553
18.2.1 AI accelerator silicon categories 553
18.2.2 Memory technology categories 553
18.2.3 Packaging terminology 553
18.2.4 Photonics terminology 554
18.2.5 Thermal terminology 554
18.2.6 Power terminology 554
18.2.7 Networking terminology 555
18.2.8 Geographic and customer terminology 555
18.3 Abbreviations 555
18.4 Sources and References 560
18.4.1 Primary research 560
18.4.2 Company financial disclosures 560
18.4.3 Industry-association and government statistics 560
18.4.4 Cross-reference industry reports 561
18.4.5 Technical and scientific literature 561
18.5 Forecast Scope, Limitations, and Disclaimers 561
18.5.1 Forecast scope 561
18.5.2 Forecast limitations 561
18.5.3 Disclaimers 562
18.6 Detailed Year-by-Year Forecast Outputs 562
圖表清單 List of Tables & Figures
List of Tables
Table 1. Headline Findings Summary (Base Case) 23
Table 2. Eleven-Year Forecast Summary: GenAI Hardware Materials Market 2026–2037 (US $B, Base Case) 25
Table 3. Top Ten Strategic Conclusions Mapped to Stakeholder Type 28
Table 4. Training vs. Inference Hardware Mix Comparison 31
Table 5. Silicon Content per 100 MW AI Training Facility (Reference BoM) 32
Table 6. Cost-per-Token by Model Size and Hardware Configuration 2024–2040 (USD per million output tokens) 33
Table 7. Sovereign AI Build-Outs by Country 2025–2030 36
Table 8. AI Accelerator Memory Requirements 2024–2030F 39
Table 9. US and Chinese Hyperscaler Capex Summary 2021–2026 (US $B) 41
Table 10. GPU Specifications: NVIDIA Blackwell, Rubin; AMD MI350X, MI450 (2024–2026) 54
Table 11. Rack-Scale GPU Platform Comparison 55
Table 12. AI ASIC Specifications: Google, AWS, Microsoft, Meta (2024–2026) 56
Table 13. AI ASIC Technology Specification Database (All Major Vendors) 59
Table 14. Chinese Data Center Processor Manufacturer Overview 62
Table 15. China AI Chip Capability Gap Assessment by Workload Type 65
Table 16. Semiconductor Process Node Roadmap 2024–2030 67
Table 17. TSMC Node Roadmap: N3, N2, A16, A14 Specs and Timeline 68
Table 18. Wafer-Scale Accelerator Yield Economics: Cerebras WSE-3 and Tesla Dojo 69
Table 19. Incumbent EDA Vendor AI Initiatives vs. Startup Cohort 126
Table 20. AI-EDA Approaches by Design-Flow Stage 127
Table 21. AI-EDA Market Forecast 2026–2037 128
Table 22. HBM Generation Technical Specifications HBM2E to HBM5 138
Table 23. HBM Bonding Integration Roadmap and Vendor Mapping 140
Table 24. HBM Market Share by Supplier 2022–2028F (%) 140
Table 25. HBM Customer Demand Breakdown: NVIDIA, Google, AMD, Hyperscalers 2024–2028F 144
Table 26. Custom HBM Players, Products, Design Roadmaps 146
Table 27. Standard vs. Custom HBM Revenue Forecast 2024–2030F (US $M) 147
Table 28. Near-Memory and In-Memory Computing Landscape 148
Table 29. Resistive Non-Volatile Memory Technologies 149
Table 30. Storage-Class Memory Technology Comparison 150
Table 31. CXL Switch Silicon Vendors and Capability Matrix 151
Table 32. 3D DRAM Technology Readiness Assessment by Player 2026 152
Table 33. Advanced Packaging Technology Comparison: 2.5D and 3D Options 177
Table 34. CoWoS Capacity Forecast by Sub-Variant 2024–2037 (k wafers/month equivalent) 180
Table 35. TSMC SoIC Variants: Specifications and AI Customer Adoption 182
Table 36. Comparative Advanced Packaging Roadmap: TSMC vs. Intel vs. Samsung 183
Table 37. Substrate Suppliers for AI Accelerator Packages 183
Table 38. Substrate Demand Forecast for AI Packages 2024–2037 (k units/month) 184
Table 39. Interposer Material Comparison: Silicon TSV vs. Glass vs. Organic RDL 185
Table 40. Hybrid Bonding Adoption Roadmap for DRAM Applications 2023–2030 185
Table 41. OSAT Capacity and Revenue Concentration 2024–2030 186
Table 42. Advanced Packaging Materials Suppliers 187
Table 43. Migration Trajectory from Copper to Optical Across the Two Network Layers 246
Table 44. Key Technology Building Blocks for Co-Packaged Optics 246
Table 45. TSMC Photonics Packaging Capabilities 247
Table 46. Merchant Photonics Packaging Platform Comparison 248
Table 47. Optical I/O Chiplet Vendor Comparison 249
Table 48. AI-Switch Silicon Roadmap with CPO Integration 250
Table 49. Silicon Photonics Foundry Capability Matrix 251
Table 50. CPO Supply Chain Critical Materials and Suppliers 252
Table 51. Photonics Packaging Revenue Forecast for AI Applications 2024–2037 (US $B) 253
Table 52. Cooling Technologies for High-Performance AI Processors 282
Table 53. Thermal Interface Material Categories and Suppliers 283
Table 54. TIM Properties for AI Accelerator Applications 284
Table 55. TIM Revenue Forecast for AI Datacenter Applications 2024–2037 (US $M) 285
Table 56. Heat Spreader and Vapor Chamber Suppliers 285
Table 57. Heat Spreader and Heat Sink Revenue Forecast 2024–2037 (US $M) 286
Table 58. Cold Plate Suppliers for AI Servers 286
Table 59. Liquid Cooling Adoption Share in New AI Datacenter Deployments 287
Table 60. Immersion Cooling Fluid Categories and Suppliers 289
Table 61. Immersion Cooling System Suppliers 289
Table 62. Microfluidic Cooling Technology Comparison 290
Table 63. Facility Liquid Cooling Infrastructure Suppliers 291
Table 64. AI-Tied Thermal Management Revenue Forecast 2024–2037 (US $B) 292
Table 65. Power Delivery Hierarchy in AI Servers 334
Table 66. Comparison of 48V and 800V HVDC Rack Architectures 335
Table 67. SiC vs. GaN vs. Silicon Power Device Comparison 336
Table 68. SiC Substrate and Device Suppliers 336
Table 69. GaN Device Manufacturers and Application Focus 338
Table 70. AI VRM Controller and Power Stage Suppliers 340
Table 71. Server Power Supply Unit Suppliers 341
Table 72. Backside Power Delivery Adoption Roadmap 342
Table 73.AI Datacenter Power Semiconductor Revenue Forecast 2024–2037 (US $B) 343
Table 74. The Three Networking Layers in an AI Datacenter 386
Table 75. AI Switch Silicon Roadmap 386
Table 76. Optical Transceiver Form Factor and Data Rate Roadmap 388
Table 77. Optical Transceiver Module Suppliers for AI Datacenters 388
Table 78. Optical DSP Suppliers and Application Mapping 390
Table 79. III-V Substrate Materials Suppliers for AI Optical Transceivers 391
Table 80. NIC, DPU, and SmartNIC Suppliers 392
Table 81. Cable, Connector, and Fiber Suppliers for AI Datacenters 392
Table 82. AI-Tied Networking and Optical Revenue Forecast 2024–2037 (US $B) 394
Table 83. AI Datacenter CAPEX Breakdown (100 MW Training Facility, 2026 Reference) 431
Table 84. Hyperscaler Power Procurement Strategies (2025 Snapshot) 433
Table 85. Major Switchgear, Transformer, and Power Infrastructure Suppliers 433
Table 86. Facility Cooling Infrastructure Suppliers 435
Table 87. Major AI Datacenter Construction Companies and Operators 436
Table 88. Construction Engineering and EPC Firms with Major AI Datacenter Practice 437
Table 89. PUE Targets and Achievement at Major Hyperscalers (2025) 439
Table 90. AI-Tied Datacenter Construction Supply Chain Revenue Forecast 2024–2037 (US $B) 440
Table 91. Edge AI NPU Performance by Application Segment 441
Table 92. Flagship Smartphone AI Processor Comparison (2026) 442
Table 93. Evolution of Apple Neural Engine AI Performance (2017–2026) 443
Table 94. AI PC Silicon Platform Comparison (2026) 444
Table 95. AI PC On-Device LLM Inference Capability (2026) 444
Table 96. NVIDIA Jetson Product Line (2026) 445
Table 97. Automotive AI Silicon Platforms (2026) 446
Table 98. Humanoid Robot Compute Platforms (2026) 447
Table 99. Edge AI Start-up Landscape 448
Table 100. Edge AI Memory Suppliers and Categories 449
Table 101. Edge AI Silicon Revenue Forecast 2024–2037 (US $B) 450
Table 102. Regional Capture of GenAI Hardware Bill of Materials, 2026 Base Case 502
Table 103. Taiwan AI Hardware Supply Chain by Capability Layer 503
Table 104. Korea AI Hardware Supply Chain by Capability Layer 504
Table 105. Japan AI Hardware Supply Chain by Capability Layer 505
Table 106. China AI Hardware Supply Chain by Capability Layer 507
Table 107. Southeast Asia and India AI Hardware Supply Chain 508
Table 108. United States AI Hardware Supply Chain by Capability Layer 509
Table 109. Europe and Israel AI Hardware Supply Chain 510
Table 110. Regional GenAI Hardware BoM Capture by Scenario (% of Global BoM Value) 512
Table 111. Major US Export Control Actions Affecting AI Hardware (2019–2026) 513
Table 112. Chinese Wafer-Fab Equipment Companies and Capability Status 514
Table 113. Major CHIPS Act-Funded Semiconductor Projects 516
Table 114. Critical Materials Supply Chain Concentration for AI Hardware 518
Table 115. Top Single-Point-of-Failure Risks in the GenAI Hardware Supply Chain 519
Table 116. Supply Chain Diversification Scenario Outcomes 2030 520
Table 117. Lifecycle Carbon Footprint by AI Chip Type 522
Table 118. AI Carbon Footprint Examples and Mitigation Strategies 523
Table 119. Estimated Embodied Carbon Across the AI Hardware Hierarchy 524
Table 120. Water Consumption Profile for AI Hardware Manufacturing and Operations 525
Table 121. Hyperscaler Renewable Energy and Nuclear Procurement (2025 Snapshot) 526
Table 122. Lifecycle and End-of-Life Treatment for AI Hardware 527
Table 123. Major Corporate Carbon Commitments Affecting AI Hardware Procurement 528
Table 124. Green Manufacturing Initiatives by Major Semiconductor Suppliers 529
Table 125. Forecast Methodology and Key Assumptions 531
Table 126. Total GenAI Hardware Market by Major Segment, Base Case (US $B) 532
Table 127. GenAI Hardware Aggregate Market Across Three Scenarios, 2026–2037 (US $B, excl. construction supply chain) 533
Table 128. AI Accelerator Silicon Sub-Segment Forecast 2024–2037 (US $B) 534
Table 129. HBM and AI-Tied Memory Sub-Segment Forecast 2024–2037 (US $B) 535
Table 130. Advanced Packaging Sub-Segment Forecast 2024–2037 (US $B, AI-tied) 536
Table 131. Photonics Packaging Sub-Segment Forecast 2024–2037 (US $B) 536
Table 132. Thermal Management Sub-Segment Forecast 2024–2037 (US $B, AI-tied) 537
Table 133. Power Delivery (AI Datacenter Tied) Sub-Segment Forecast 2024–2037 (US $B) 537
Table 134. Networking and Optical (AI-Tied) Sub-Segment Forecast 2024–2037 (US $B) 538
Table 135. Datacenter Construction Supply Chain Sub-Segment Forecast 2024–2037 (US $B) 539
Table 136. Edge AI Silicon Sub-Segment Forecast 2024–2037 (US $B) 539
Table 137. Regional GenAI Hardware BoM Capture Forecast, 2026–2037, Base Case (%) 539
Table 138. Total GenAI Hardware Demand by Customer Tier, Base Case 2026–2037 (US $B, excl. construction supply chain) 540
Table 139. The Five Defining Themes: Strategic Implications by Layer 543
Table 140. The Top 15 Strategic Choke Points in the GenAI Hardware Supply Chain 543
Table 141. Strategic Tier Classification of GenAI Hardware Sub-Segments 544
Table 142. Notable GenAI Hardware M&A and Strategic Investments 2020–2026 546
Table 143. Sensitivity of Base Case 2030 Forecast to Key Assumptions 547
Table 144. Detailed Year-by-Year Total Forecast, Base Case (US $B, excl. DC construction supply chain) 562
Table 145. Detailed Year-by-Year Total Forecast Across All Three Scenarios (US $B, excl. DC construction supply chain) 563
List of Figures
Figure 1. Five Compute-Scaling Walls and Their Material Solutions 24
Figure 2. Generative AI Hardware Materials Value-Chain Layer Map 25
Figure 3. Base-Case Forecast Stacked-Area Visualisation 2026–2037 26
Figure 4. Bull, Base, and Bear Scenario Comparison 2026–2037 27
Figure 5. Asia-Pacific Capture Rate of GenAI Hardware Value 2026–2037 28
Figure 6. AI Data Centre Silicon Content Map 32
Figure 7. Inference Token Economics by Model Size 34
Figure 8. Sovereign AI Capex Pipeline 2024–2030 by Geography 36
Figure 9. Generative AI Compute Demand Scaling vs. Electrical Interconnect Capacity 38
Figure 10. AI Accelerator BoM Decomposition: Where the Dollars Go 40
Figure 11. Annual GenAI-Driven AI Hardware Demand Pool 2024–2030 43
Figure 12. NVIDIA GPU Architecture Evolution: Volta to Post-Blackwell Timeline 53
Figure 13. Rack-Scale GPU Architecture: NVL72 and Next-Generation Platforms 55
Figure 14. Hyperscaler ASIC Roadmap Comparison 57
Figure 15. Hyperscaler ASIC vs. Merchant GPU Share of Datacenter AI Compute 2024–2037 59
Figure 16. AI ASIC Start-Up Landscape by Funding Stage 60
Figure 17. GPU vs. AI ASIC Performance per Watt Comparison 2022–2026 62
Figure 18. China Semiconductor Capability Map: Node vs. Supply-Chain Layer 64
Figure 19. China AI Chip Roadmap vs. NVIDIA / AMD: Parity Distance by Generation 66
Figure 20. Leading-Edge Foundry Roadmap Comparison 2023–2037 (Gantt) 67
Figure 21. HBM Architecture: Die-Stack Cross-Section 137
Figure 22. HBM Bandwidth Evolution HBM1 to HBM5 138
Figure 23. HBM4 Die-to-Wafer Bonding Integration Scheme 139
Figure 24. HBM Market Share by Supplier 2022–2028F 141
Figure 25. SK hynix HBM Strategy and Roadmap 142
Figure 26. Samsung HBM Strategy and Roadmap 143
Figure 27. Micron HBM Strategy and Roadmap 144
Figure 28. HBM Customer Demand Breakdown by AI Accelerator 145
Figure 29. Custom HBM Architecture: Co-Design Concept 146
Figure 30. Custom HBM Share of Total HBM Bit Demand 2026–2037 147
Figure 31. Near-Memory vs. PIM Architecture Comparison 149
Figure 32. CXL Memory Pooling Architecture and Vendor Map 151
Figure 33. 3D DRAM Concept Architectures 153
Figure 34. Monolithic Die vs. Chiplet Architecture: Yield and Cost 177
Figure 35. Chiplet Interconnect Technology Spectrum 179
Figure 36. CoWoS Integration: GPU + HBM on Silicon Interposer 180
Figure 37. CoWoS Capacity Expansion Roadmap 181
Figure 38. OSAT Revenue Concentration by Geography 2024–2037 187
Figure 39. Compute Demand vs. Interconnect Bandwidth Gap 245
Figure 40. Photonics Packaging Revenue Forecast for AI Applications 2024–2037 253
Figure 41. AI Accelerator TDP and Cooling Architecture Trajectory 2022–2037 283
Figure 42. Liquid Cooling Adoption Trajectory in AI Datacenter Deployments 288
Figure 43. Power Density at AI Server Rack: From 30 kW to 600 kW per Rack 334
Figure 44. Wide-Bandgap Power Semiconductor Material Properties Comparison 339
Figure 45. Edge AI Performance and Power Envelope Map 442
Figure 46. Total GenAI Hardware Market 2024–2037 by Segment, Base Case 533
Figure 47. GenAI Hardware Market Bull/Base/Bear Scenarios 2024–2037 534
Figure 48. Sensitivity of 2030 Forecast to Key Variables 548
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